1. Field of the Invention
The present invention relates to a base-pad for a polishing pad that polishes electrical devices such as semiconductor devices, memory disks or the like, having a variety of substrates, including but not limited to silicon, silicon dioxide, metals, metal oxide, dielectrics (including polymeric dielectrics), ceramics, glass and the like.
2. Discussion of Related Art
CMP (chemical-mechanical polishing or chemical-mechanical planarization) is a manufacturing process performed by a polishing pad in combination with a polishing fluid to polish, for example, a silicon wafer having metal circuits embedded in trenches in a substrate of the wafer. The polishing pad is mounted on a platen of a known polishing apparatus. A base-pad is positioned between the polishing pad and the platen.
A conventional base-pad is formed from foamed sheets or felts impregnated with a polymeric material. However, such a base-pad is too compliant when subjected to the forces occurring during a polishing operation, which can cause the pad to settle into recesses in the substrate that is being polished, which, in turn, causes excessive polishing. As a result, the surfaces of the embedded circuits become polished excessively, causing unwanted recesses known as dishing. Further, such a base-pad absorbs polishing fluid, and is compressed during a polishing operation such that it becomes deformed in all directions, causing the pad to become too compliant. A measure of the compressibility in such different directions provides a prediction that the base-pad will deform in such different directions due to the application of forces.
U.S. Pat. No. 5,212,910 discloses a composite polishing pad having a soft elastomeric material, a hard material such as an epoxy fiberglass composition as an intermediate layer, and a spongy material as the polishing surface.
U.S. Pat. No. 5,257,478 discloses a polishing pad with a resilient layer having a hydrostatic modulus different from that of a polishing layer.
U.S. Pat. No. 5,871,392 discloses an under pad, placed between the platen and a polishing pad, containing a plurality of thermal conductors to reduce temperature gradients across the planarizing surface of the polishing pad.
U.S. Pat. No. 5,287,663 discloses a polishing pad having a rigid layer adjacent to the polishing layer. The rigid layer imparts a controlled rigidity to the polishing layer.
U.S. Pat. No. 5,899,745 discloses an under pad that is positioned under a conventional CMP pad, and having regions of different hardness between the center and the exterior portions of the pad for final wafer profile control.
The present invention is directed to a base-pad, and to a combination of the base-pad and a polishing pad to provide a high level of planarity and low non-uniformity while polishing. The base-pad of this invention comprises a layer of an anisotropic structure having vertical elongated pores. Minimal polishing fluid absorption is limited to absorption by the vertical elongated pores, which minimizes lateral transport of absorbed polishing fluid, thereby greatly reducing polishing fluid wicking laterally in the pad during polishing, and which minimizes any change in compressibility of the base-pad and the polishing pad. Further, the anisotropic structure is microporous, having pores that are impervious to the polishing fluid, but are permeable to entrapped gaseous atmosphere, which allows escape of gasses that tend to become entrapped in the base-pad absorbed with polishing fluid. The base-pad of this invention in combination with a polishing pad will polish a semiconductor wafer with a high degree of planarity and a low degree of non-uniformity due to dishing.